The present invention relates in general to semiconductor devices for use in integrated circuits (ICs). More specifically, the present invention relates to improved fabrication methods and resulting structures for the co-integration of high carrier (e.g., holes) mobility p-type field effect transistors (PFETs) and high carrier (e.g., electrons) mobility n-type field effect transistors (NFETs) on the same substrate using a low temperature (e.g., a temperature<about 550 Celsius) condensation process.
Transistors are fundamental device elements of modern digital processors and memory devices. A transistor type that has emerged within the metal-oxide-semiconductor field-effect transistor (MOSFET) family of transistors, and which shows promise for scaling to ultra-high density and nanometer-scale channel lengths, is a so-called fin-type FET (FinFET) device. FinFETs are non-planar, three-dimensional (3D) devices that include a fin-shaped channel with a gate formed along the sidewalls and top surface of the fin channel.
Although forming the fin channel from silicon (Si) provides benefits, forming the fin channel from materials other than Si can provide higher carrier mobility in the channel. For example, to provide a higher carrier mobility than Si, it has been proposed to form the fin channel of a p-type FinFET from silicon germanium (SiGe), and form the fin channel of an n-type FinFET from III-V compound materials. III-V compound semiconductors are obtained by combining group III elements (e.g., Al, Ga, In) with group V elements (e.g., N, P, As, Sb). In addition to improving carrier mobility, channels formed from SiGe or III-V compound materials introduce strain at the interface between the SiGe or III-V material and the underlying Si substrate.